As is known, a memory controller manages the flow of data going to and from the memory of a computing system. A memory controller can be implemented on the system's motherboard (e.g. in the northbridge of a northbridge-southbridge configuration), or even directly on the system's CPU die to reduce the memory latency. In any such cases, memory controllers typically include logic for reading and writing dynamic RAM (DRAM), as well as the requisite refresh circuitry.
Memory controllers generally include a number of memory channels. Each channel communicates to DRAM devices installed on dual in-line memory modules (DIMMs). Memory controllers traditionally issue a system cache line request to one channel, using a data burst-length of 8 transfers. Channel width is 8 bytes, resulting in a 64 byte cache line transfer. Alternatively, memory controllers can issue a system cache line request to two channels simultaneously using a data burst-length of 4 (with channel width still at 8 bytes). This transfers 32 bytes per channel, simultaneously, resulting in the 64 bytes cache line. In such dual channel configurations, the channels are said to operate in lockstep.
An advantage of obtaining 64 bytes from 2 lockstep channels is that the payload data resides in twice as many DRAM devices. This allows chip-fail error correction code (ECC) algorithms to be used in the system for a wider variety of DRAM devices. These chip-fail algorithms require transferring payload data from either 16 or 32 DRAM devices, or 18 or 36 devices when including the ECC devices. A disadvantage of lockstep channels is the data burst-length of 4. This incurs a performance penalty for the system, because the data transfer duration on the channel is short compared to bus electrical turnarounds. In addition, new DRAM devices like double-data-rate three (DDR3) are optimized for a burst-length of 8, and incur additional performance penalties when used in burst-length 4 mode.
What is needed, therefore, are memory controllers for dual channel lockstep configurations.